ADSP-21368BBP-2A中文資料亞德諾數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

GENERAL DESCRIPTION

The ADSP-21367/ADSP-21368/ADSP-21369 SHARC? processors are members of the SIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. These processors are source code-compatible with the ADSP-2126x and ADSP-2116x DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. The processors are 32-bit/40-bit floating-point processors optimized for high performance automotive audio applications with its large on-chip SRAM, and mask programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital audio interface (DAI).

SUMMARY

High performance 32-bit/40-bit floating-point processor

optimized for high performance audio processing

Single-instruction, multiple-data (SIMD) computational

architecture

On-chip memory—2M bits of on-chip SRAM and 6M bits of

on-chip mask programmable ROM

Code compatible with all other members of the SHARC family

The ADSP-21367/ADSP-21368/ADSP-21369 are available

with a 400 MHz core instruction rate with unique audiocentric

peripherals such as the digital audio interface, S/PDIF

transceiver, serial ports, 8-channel asynchronous sample

rate converter, precision clock generators, and more. For

complete ordering information, see Ordering Guide on

Page 55.