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MC54SLASH74HC533A中文資料摩托羅拉數(shù)據(jù)手冊(cè)PDF規(guī)格書
| 廠商型號(hào) |
MC54SLASH74HC533A |
| 功能描述 | OCTAL 3-STATE INVERTING TRANSPARENT LATCH HIGH-PERFORMANCE SILICON-GATE CMOS |
| 文件大小 |
92.49 Kbytes |
| 頁面數(shù)量 |
7 頁 |
| 生產(chǎn)廠商 | Motorola, Inc |
| 企業(yè)簡稱 |
MOTOROLA【摩托羅拉】 |
| 中文名稱 | 加爾文制造公司官網(wǎng) |
| 原廠標(biāo)識(shí) |  |
| 數(shù)據(jù)手冊(cè) | |
| 更新時(shí)間 | 2025-5-30 12:00:00 |
| 人工找貨 | MC54SLASH74HC533A價(jià)格和庫存，歡迎聯(lián)系客服免費(fèi)人工找貨 |
MC54SLASH74HC533A規(guī)格書詳情
Octal 3-State Inverting Transparent Latch
High–Performance Silicon–Gate CMOS
The MC54/74HC533A is identical in pinout to the LS533. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. The Data appears at the outputs in inverted form. When Latch Enable goes low, data meeting the setup and hold time becomes latched.
? Output Drive Capability: 15 LSTTL Loads
? Outputs Directly Interface to CMOS, NMOS and TTL
? Operating Voltage Range: 2.0 to 6.0 V
? Low Input Current: 1.0 μA
? High Noise Immunity Characteristic of CMOS Devices
? In Compliance with the Requirements Defined by JEDEC Standard No. 7A
? Chip Complexity: 256 FETs or 64 Equivalent Gates
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24+ |
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5000 |
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228 |
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Module |
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SOT-23 |
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6523 |
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21+ |
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12588 |
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3000 |
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100500 |
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詢價(jià) |
