MIMXRT102ADFP4A中文資料恩智浦?jǐn)?shù)據(jù)手冊PDF規(guī)格書

Features

The i.MX RT1060X processors are based on Arm Cortex-M7 Core Platform, which has the following features:

?Supports single Arm Cortex-M7 Core with:

-32 KB L1 Instruction Cache

-32 KB L1 Data Cache

-Full featured Floating Point Unit (FPU) with support of the VFPv5 architecture

-Support the Armv7-M Thumb instruction set

?Integrated MPU, up to 16 individual protection regions

?Tightly coupled GPIOs, operating at the same frequency as Arm Core

?Up to 512 KB I-TCM and D-TCM in total

?Frequency of 600 MHz

?Cortex M7 CoreSight? components integration for debug

?Frequency of the core, as per Table 9.

The SoC-level memory system consists of the following additional components:

?Boot ROM (128 KB)

?On-chip RAM (1 MB)

-512 KB OCRAM shared between ITCM/DTCM and OCRAM

-Dedicate 512 KB OCRAM

?External memory interfaces:

-8/16-bit SDRAM, up to SDRAM-133/SDRAM-166

-8/16-bit SLC NAND FLASH, with ECC handled in software

-SD/eMMC

-SPI NOR/NAND FLASH

-Parallel NOR FLASH with XIP support

-Two single/dual channel Quad SPI FLASH with XIP support

?Timers and PWMs:

-Two General Programmable Timers (GPT)

?4-channel generic 32-bit resolution timer for each

?Each support standard capture and compare operation

-Four Periodical Interrupt Timers (PIT)

?Generic 32-bit resolution timer

?Periodical interrupt generation

-Four Quad Timers (QTimer)

?4-channel generic 16-bit resolution timer for each

?Each support standard capture and compare operation

?Quadrature decoder integrated

-Four FlexPWMs

?Up to 8 individual PWM channels per each

?16-bit resolution PWM suitable for Motor Control applications

-Four Quadrature Encoder/Decoders

Each i.MX RT1060X processor enables the following interfaces to external devices (some of them are muxed and not available simultaneously):

?Display Interface:

-Parallel RGB LCD interface

?Support 8/16/24 bit interface

?Support up to WXGA resolution

?Support Index color with 256 entry x 24 bit color LUT

?Smart LCD display with 8/16-bit MPU/8080 interface

?Audio:

-S/PDIF input and output

-Three synchronous audio interface (SAI) modules supporting I2S, AC97, TDM, and codec/DSP interfaces

-MQS interface for medium quality audio via GPIO pads

?Generic 2D graphics engine:

-BitBlit

-Flexible image composition options-alpha, chroma key

-Porter-duff blending

-Image rotation (90°, 180°, 270°)

-Image size

-Color space conversion

-Multiple pixel format support (RGB, YUV444, YUV422, YUV420, YUV400)

-Standard 2D-DMA operation

?Camera sensors:

-Support 24-bit, 16-bit, and 8-bit CSI input

?Connectivity:

-Two USB 2.0 OTG controllers with integrated PHY interfaces

-Two Ultra Secure Digital Host Controller (uSDHC) interfaces

?MMC 4.5 compliance with HS200 support up to 200 MB/sec

?SD/SDIO 3.0 compliance with 200 MHz SDR signaling to support up to 100 MB/sec

?Support for SDXC (extended capacity)

-Two 10/100M Ethernet controllers with support for IEEE1588

-Eight universal asynchronous receiver/transmitter (UARTs) modules

-Four I2C modules

-Four SPI modules

-Two FlexCAN modules

-One FlexCAN (with Flexible Data-Rate supported)

-Three FlexIO modules

?GPIO and Pin Multiplexing:

-General-purpose input/output (GPIO) modules with interrupt capability

-Input/output multiplexing controller (IOMUXC) to provide centralized pad control

The i.MX RT1060X processors integrate advanced power management unit and controllers:

?Full PMIC integration, including on-chip DCDC and LDO

?Temperature sensor with programmable trim points

?GPC hardware power management controller

The i.MX RT1060X processors support the following system debug:

?Arm CoreSight debug and trace architecture

?Trace Port Interface Unit (TPIU) to support off-chip real-time trace

?Cross Triggering Interface (CTI)

?Support for 5-pin (JTAG) and SWD debug interfaces

The i.MX RT1060X processors support the following analog interfaces:

?Two Analog-Digital-Converters (ADC), 16-channel for each, 20-channel in total

?Four Analog Comparators (ACMP)

Security functions are enabled and accelerated by the following hardware:

?High Assurance Boot (HAB)

?Data Co-Processor (DCP):

-AES-128, ECB, and CBC mode

-SHA-1 and SHA-256

-CRC-32

?Bus Encryption Engine (BEE)

-AES-128, ECB, and CTR mode

-On-the-fly QSPI Flash decryption

?True random number generation (TRNG)

?Secure Non-Volatile Storage (SNVS)

-Secure real-time clock (RTC)

-Zero Master Key (ZMK)

?Secure JTAG Controller (SJC)