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PCA9541APW/03中文資料恩XP數(shù)據(jù)手冊PDF規(guī)格書

PCA9541APW/03
廠商型號

PCA9541APW/03

功能描述

2-to-1 I2C-bus master selector with interrupt logic and reset

絲印標識

9541A/3

封裝外殼

TSSOP16

文件大小

383.93 Kbytes

頁面數(shù)量

45

生產(chǎn)廠商 未知制造商
企業(yè)簡稱

恩XP

中文名稱

未知制造商

原廠標識
數(shù)據(jù)手冊

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更新時間

2025-5-29 15:23:00

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PCA9541APW/03規(guī)格書詳情

General description

The PCA9541A is a 2-to-1 I2C-bus master selector designed for high reliability dual

master I2C-bus applications where system operation is required, even when one master

fails or the controller card is removed for maintenance. The two masters (for example,

primary and back-up) are located on separate I2C-buses that connect to the same

downstream I2C-bus slave devices. I2C-bus commands are sent by either I2C-bus master and are used to select one master at a time. Either master at any time can gain control of the slave devices if the other master is disabled or removed from the system. The failed master is isolated from the system and does not affect communication between the on-line master and the slave devices on the downstream I2C-bus.

Two versions are offered for different architectures. PCA9541A/01 with channel 0

selected at start-up, and PCA9541A/03 with no channel selected after start-up.

The interrupt outputs are used to provide an indication of which master has control of the bus. One interrupt input (INT_IN) collects downstream information and propagates it to the 2 upstream I2C-buses (INT0 and INT1) if enabled. INT0 and INT1 are also used to let the previous bus master know that it is not in control of the bus anymore and to indicate the completion of the bus recovery/initialization sequence. If the masking option is set, those interrupts can be disabled and do not generate an interrupt.

A bus recovery/initialization if enabled sends nine clock pulses, a not acknowledge, and a

STOP condition in order to set the downstream I2C-bus devices to an initialized state

before actually switching the channel to the selected master. An interrupt is sent to the upstream channel when the recovery/initialization procedure is completed. An internal bus sensor senses the downstream I2C-bus traffic and generates an interrupt if a channel switch occurs during a non-idle bus condition. This function is enabled when

the PCA9541A recovery/initialization is not used. The interrupt signal informs the master

that an external I2C-bus recovery/initialization must be performed. It can be disabled and an interrupt is not generated. The pass gates of the switches are constructed such that the VDD pin can be used to limit the maximum high voltage, which will be passed by the PCA9541A. This allows the use of different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V devices can communicate with 5 V devices without any additional protection. The PCA9541A does not isolate the capacitive loading on either side of the device, so the designer must take into account all trace and device capacitances on both sides of the device, and pull-up resistors must be used on all channels. External pull-up resistors pull the bus to the desired voltage level for each channel. All I/O pins are 6.0 V tolerant.An active LOW reset input allows the PCA9541A to be initialized. Pulling the RESET pin LOW resets the I2C-bus state machine and configures the device to its default state as does the internal Power-On Reset (POR) function.

Features and benefits

? 2-to-1 bidirectional master selector

? I2C-bus interface logic; compatible with SMBus standards

? PCA9541A/01 powers up with Channel 0 selected

? PCA9541A/03 powers up with no channel selected and either master can take control

of the bus

? Active LOW interrupt input

? 2 active LOW interrupt outputs

? Active LOW reset input

? 4 address pins allowing up to 16 devices on the I2C-bus

? Channel selection via I2C-bus

? Bus initialization/recovery function

? Bus traffic sensor

? Low Ron switches

? Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses

? No glitch on power-up

? Supports hot insertion

? Software identical for both masters

? Low standby current

? Operating power supply voltage range of 2.3 V to 5.5 V

? 6.0 V tolerant inputs

? 0 Hz to 400 kHz clock frequency

? ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per

JESD22-C101

? Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

? Packages offered: SO16, TSSOP16, HVQFN16

供應(yīng)商 型號 品牌 批號 封裝 庫存 備注 價格
恩XP
25+
原廠封裝
10280
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詢價
恩XP
24+
TSSOP
80000
只做自己庫存,全新原裝進口正品假一賠百,可開13%增
詢價
恩XP
24+
TSSOP16
9600
原裝現(xiàn)貨,優(yōu)勢供應(yīng),支持實單!
詢價
恩XP
24+
N/A
6000
原裝,正品
詢價
恩XP
23+
N/A
6000
公司只做原裝,可來電咨詢
詢價
恩XP
22+
NA
2400
原裝正品支持實單
詢價
恩XP
24+
TSSOP
4000
原裝原廠代理 可免費送樣品
詢價
恩XP
24+
TSSOP-16
5524
原裝正品,現(xiàn)貨庫存,1小時內(nèi)發(fā)貨
詢價
恩XP
23+
NA
6000
原裝現(xiàn)貨訂貨價格優(yōu)勢
詢價
恩XP
24+
TSSOP16
39500
進口原裝現(xiàn)貨 支持實單價優(yōu)
詢價