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首頁(yè) >SSTU32865ET/G>規(guī)格書列表

零件編號(hào)	下載訂購(gòu)	功能描述/絲印	制造商上傳企業(yè)	LOGO
ICSSSTUAF32865A	文件：676.61 Kbytes Page：17 Pages	28-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2 Features ?28-bit1:2registeredbufferwithparitycheckfunctionality ?SupportsSSTL_18JEDECspecificationondatainputs andoutputs ?SupportsLVCMOSswitchinglevelsonCSGateENand RESETinputs ?Lowvoltageoperation:VDD=1.7Vto1.9V ?Availablein160-ballLFBGApackage Applic	RENESASRenesas Technology Corp 瑞薩瑞薩科技有限公司	RENESAS
ICSSSTUAF32865A	文件：422.3 Kbytes Page：17 Pages	25-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2 Description This28-bit1:2registeredbufferwithparityisdesignedfor1.7Vto1.9VVDDoperation. AllclockanddatainputsarecompatiblewiththeJEDECstandardforSSTL_18.ThecontrolinputsareLVCMOS.Alloutputsare1.8VCMOSdriversthathavebeenoptimizedtodrivetheDDR2DIMMlo	IDT Integrated Device Technology, Inc.	IDT
ICSSSTUAF32865AHLFT	文件：422.3 Kbytes Page：17 Pages	25-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2 Description This28-bit1:2registeredbufferwithparityisdesignedfor1.7Vto1.9VVDDoperation. AllclockanddatainputsarecompatiblewiththeJEDECstandardforSSTL_18.ThecontrolinputsareLVCMOS.Alloutputsare1.8VCMOSdriversthathavebeenoptimizedtodrivetheDDR2DIMMlo	IDT Integrated Device Technology, Inc.	IDT
ICSSSTUAF32865AHLFT	文件：676.61 Kbytes Page：17 Pages	28-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2 Features ?28-bit1:2registeredbufferwithparitycheckfunctionality ?SupportsSSTL_18JEDECspecificationondatainputs andoutputs ?SupportsLVCMOSswitchinglevelsonCSGateENand RESETinputs ?Lowvoltageoperation:VDD=1.7Vto1.9V ?Availablein160-ballLFBGApackage Applic	RENESASRenesas Technology Corp 瑞薩瑞薩科技有限公司	RENESAS
ICSSSTUAH32865A	文件：418.77 Kbytes Page：17 Pages	25-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2 Description This28-bit1:2registeredbufferwithparityisdesignedfor1.7Vto1.9VVDDoperation. AllclockanddatainputsarecompatiblewiththeJEDECstandardforSSTL_18.ThecontrolinputsareLVCMOS.Alloutputsare1.8VCMOSdriversthathavebeenoptimizedtodrivetheDDR2DIMMlo	IDT Integrated Device Technology, Inc.	IDT
ICSSSTUAH32865AHLFT	文件：418.77 Kbytes Page：17 Pages	25-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2 Description This28-bit1:2registeredbufferwithparityisdesignedfor1.7Vto1.9VVDDoperation. AllclockanddatainputsarecompatiblewiththeJEDECstandardforSSTL_18.ThecontrolinputsareLVCMOS.Alloutputsare1.8VCMOSdriversthathavebeenoptimizedtodrivetheDDR2DIMMlo	IDT Integrated Device Technology, Inc.	IDT
SSTU32865	文件：157.04 Kbytes Page：29 Pages	1.8V28-bit1:2registeredbufferwithparityforDDR2RDIMM	PhilipsPhilips Semiconductors 飛利浦荷蘭皇家飛利浦	Philips
SSTU32865EG	文件：157.04 Kbytes Page：29 Pages	1.8V28-bit1:2registeredbufferwithparityforDDR2RDIMM	PhilipsPhilips Semiconductors 飛利浦荷蘭皇家飛利浦	Philips
SSTU32865ET	文件：157.04 Kbytes Page：29 Pages	1.8V28-bit1:2registeredbufferwithparityforDDR2RDIMM	PhilipsPhilips Semiconductors 飛利浦荷蘭皇家飛利浦	Philips
SSTUH32865	文件：154.01 Kbytes Page：28 Pages	1.8V28-bithighoutputdrive1:2registeredbufferwithparityforDDR2RDIMMapplications	PhilipsPhilips Semiconductors 飛利浦荷蘭皇家飛利浦	Philips

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